Memory Buffer
| DDR2 Advanced Memory Buffer (AMB) |
| M88MB2000/1 |
| M88MB3000/1 |
| DDR3 Register Buffer |
| M88SSTE32882 |
M88SSTE32882 – DDR3 Registered Buffer with Parity and Quad Chip Selects The M88SSTE32882 is a 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 configurable registering clock driver with parity for 1.5 V or 1.35 V VDD operation. The device accepts 28 bits or 26 bits of address and control signals and outputs two copies per signal. Based on control register settings the device can change its output characteristics to match different DIMM net topologies. The timing can be changed to compensate for different flight time of signals within the target application. By disabling unused outputs the power consumption is reduced. The M88SSTE32882 is fully compliant with the JEDEC standard. In addition, it provides an extra register read mechanism (patent-pending) beyond the JEDEC spec to enable the status monitoring of the device without changing its existing pinout. Further, the host software modification is minimized via enabling read operations through write operations.
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