Montage Technology(Shanghai) Co.,Ltd

M88SSTE32882 – DDR3 Registered Buffer with Parity and Quad Chip Selects

The M88SSTE32882 is a 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 configurable registering clock driver with parity for 1.5 V or 1.35 V VDD operation.

The device accepts 28 bits or 26 bits of address and control signals and outputs two copies per signal. Based on control register settings the device can change its output characteristics to match different DIMM net topologies. The timing can be changed to compensate for different flight time of signals within the target application. By disabling unused outputs the power consumption is reduced.

The M88SSTE32882 is fully compliant with the JEDEC standard. In addition, it provides an extra register read mechanism (patent-pending) beyond the JEDEC spec to enable the status monitoring of the device without changing its existing pinout. Further, the host software modification is minimized via enabling read operations through write operations.

Feature

	•	Fully compliant with JEDEC SSTE32882 standard
	•	28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registered buffer for address and control signals
	•	Quad chip selects support
	•	Dual VDD voltage support: 1.5 V / 1.35 V
	•	Register read operation support (patent pending)
	•	S3 low power mode support
	•	1T/3T MRS timing support
	•	Pre-launch feature support
	•	DDR3-800/1066/1333/1600 SDRAM support
	•	Integrated PLL clock driver distributing one differential clock pair to four differential pairs
	•	Constant propagation delay with VT variations
	•	1.5 V CMOS compatible clock and data inputs
	•	1.5 V CMOS outputs
	•	Parity checking on command and address data inputs
	•	Output characteristics configurable through control registers
	•	Different power saving modes support
	•	3.5 mW power consumption in CK stop mode
	•	Green package: 176-ball TFBGA

Application

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High-performance DDR3 RDIMM server

For detailed information about the products, please contact Montage Sales.

Tel: +86 21 51696833
Email: sales@montage-tech.com