JOB DESCRIPTION:
- Involve in various stages of IC product development: Participate in RTL, design, verification, synthesis, timing analysis, test pattern generation, backend verification and silicon debug.
- Involve in all stages of IC product development including specification, definition, RTL, design, whole chip verification, synthesis, timing analysis, test pattern generation, backend verification and silicon debug.
QUALIFICATIONS:
- BSEE with minimum 5-year or MSEE with minimum 3-year of experience designing integrated circuits.
- Solid knowledge of ASIC design flow using Verilog/VHDL and EDA tools such as Cadence Verilog_XL/NC-Sim, Synopsys, DC, PT, etc.
- Solid knowledge of DFT structural test and multi-domain clock design methodology in million gates SoC level chip design.
- Project leading and product definition experience is preferred.
- Experience with MPEG decoder and Digital Image processing is a plus.