Social Recruitment

JOB DESCRIPTION：

  • PCIE driver development
  • Memory management and page table sync with other CPU
  • API support to customer’s application software

QUALIFICATION：

  • MSEE with 8+ year experience or PhD with 5+ year experience
  • Experience with Linux kernel and driver development for x86 or ARM server
  • Experience with PCIE device related software design
  • Self-motivated, good team work spirit and good communication skills

 

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JOB DESCRIPTION:

We are looking for an experienced Switch Power IC design engineer to develop a high efficiency Buck PMIC for next generation  DDR application. The Job includes but not limits to below items:

  • Buck behavior model build up, key parameters simulation, fine tune and verification
  • Define specifications of  blocks and create design documentation
  • All function block circuit level design, simulation and verification
  • Supervise layout floor plan and design of each function blocks
  • Silicon evaluation test, characterization and debugging
  • Production test development support

QUALIFICATION:

  • BSEE or above with at least 2 years of experience in switch power IC development
  • Experience in switch power supply behavior model build up
  • Experience in Buck power IC circuit design
  • Ability to supervise layout floor plan and design
  • Good understanding of BCD process, model for switch power supply IC design
  • Proficiency of EDA design tools (Simplis, Spectre, HSPICE, etc.)
  • Good Lab experience in switch power IC testing
  • Good verbal and written communication and presentation skills, positive attitude
  • Willing to take challenges and to solve difficult technical problems
  • Quick learner

 

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JOB DESCRIPTION:

  • Write Micro-Architecture Definition/Writing Design Implementation Spec
  • Write RTL coding for block or top level
  • Do IP level synthesis / timing analysis / formality check / CDC check /Code coverage check
  • Assist on Verification Engineer to complete module and top level simulation and verification
  • Debug RTL/Gate Level waveform at module or top level
  • Do Silicon debugging of the related module functionalities and provide ECO solution accordingly

QUALIFICATION:

  • MSEE with 5~6 year experience of digital design experience
  • Relevant experience in high speed IO IP design, and PCIe design experience is a big plus
  • Very Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO
  • Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
  • Strong skills of Script and be familiar with TCL, Perl, etc.
  • Self-motivated, good team work spirit and good communication skills

Apply

JOB DESCRIPTION:

  • Validate, debug, and understand PCIe link training (LTSSM), Data Link Layer (DLLP), and Transaction Layer (TLP)
  • Plan, develop, and execute post-silicon validation plans
  • System level debugging of post-silicon hardware and software issues
  • Build and support validation infrastructure through the development of embedded software, device drivers, and test tools

 

    QUALIFICATION:

    Required:

    • Bachelor or Master degree in CS, CE, EE with 7+ years
    • Knowledge of PCI/PCI Express system architecture
    • Excellent knowledge of PCIe link training (LTSSM), Data Link Layer (DLLP), and Transaction Layer (TLP)
    • Experience with PCIe Analyzers / Exercisers
    • Proficient in Python/ C programming
    • Ability to develop functional validation plans and develop software necessary to execute these plans

    Preferred:

    • Excellent knowledge of digital systems and computer architecture
    • Experience developing device drivers for Windows or Linux
    • Experience in use of lab equipment (e. g., protocol analyzers/exercisers)
    • Excellent verbal and written communication skills

     

    Apply

    JOB DESCRIPTION:

    • Implement DFT related designs including scan, JTAG, MBIST and Analog Macro test
    • Develop and enhance DFT flow 
    • Work with design team for DFT integration
    • Generate DFT related timing constraints and work with backend team to close DFT timing and power
    • Work with test engineering team in patterns handoff and silicon bring up 

    QUALIFICATIONS:

    • BSEE/MSEE with 5+ years of industry experience in DFT
    • Good understanding of scan/ATPG, JTAG, MBIST, boundary scan and other DFT techniques
    • Proficient with scripting, such as TCL, Python and Perl 
    • Good understanding of DFT timing and power
    • Self-driven, good team work spirit and good communication skills

     

    Apply

    JOB DESCRIPTION:

    • Discuss with software engineers to understand their requirements of DSP
    • Write Micro-Architecture definition of DSP subsystem
    • Selection and configuration of DSP cores
    • RTL integration of multiple DSP cores, RAM instances, FIFO, DMA engine to form DSP subsystem
    • Synthesis/timing analysis/formality check/CDC check/Code coverage check of DSP subsystem
    • Assist on Verification Engineer to complete module and top level simulation and verification
    • Debug RTL/Gate Level waveform at module or top level
    • Do Silicon debugging of the related module functionalities and provide ECO solution accordingly

    QUALIFICATION:

    • MSEE with 8+ year experience or PhD with 6+ year experience of digital design
    • Strong knowledge of DSP including SIMD, vector operations, data loading & store organization
    • Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO
    • At least 3+ year experience in DSP design or integration
    • At least 3+ year experience in AXI/AHB/APB protocols and ARM-based fabric design
    • Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys VCS, DC, PT, etc.
    • Basic skills of Script and be familiar with TCL, Perl, etc.
    • Self-motivated, good team work spirit and good communication skills

     

    Apply

    JOB DESCRIPTION:

    • Linux and other OS enabling on ARM or RISC-V based processors
    • Kernel module and driver development for PCIE based devices
    • PCIE, DDR and other interface enabling
    • System verification and testing for SoC device and module for server system

    QUALIFICATION:

    • MSEE with 8+ year experience or PhD with 5+ year experience
    • In depth knowledge of ARM or RISC-V CPU and embedded system programming
    • Experience with Linux kernel and driver development
    • Experience with x86 server system design/optimization is a plus
    • Strong programming and optimization skills
    • Self-motivated, good team work spirit and good communication skills

     

    Apply