- Lead physical design of projects, build and manage physical design team;
- Coordinate with different teams to close design issues, such as front-end team, DFT team, and package team;
- Responsible for achievable die size, meet design requirements, drive design closure and sign-off checks;
- Responsible for full chip floorplan & partition, pin assign, feedthrough & repeater insertion; release floorplan to block level implementation;
- Develop top level physical design flow.
- Bachelor or Master Degree in Engineering (Microelectronics, Electronics);
- 10+ years of hands on experience in large scale ASIC chip physical design;
- Experienced with large scale full chip floorplan;
- Familiar with top-down design methodology;
- Experience on project and team management;
- Good teamwork and communication skills;
- Proficient with scripting/programming (TCL, Perl, shell script, Python);
- Language: Good English read/write.
- Working with chip design teams to validate the performance of high speed Serdes chips;
- Perform Serdes signal integrity related measurement on RD phase, including S parameters, impedance, eyes, all kinds of jitters and noise, JTOL, bathtub curve, phase jitter;
- Perform the compliance test according to the PCIe and 802.3 standards;
- Writing Python codes to conduct automatic measurement on Serdes transmitter, receiver and system board;
- Debug problems together with chip design teams.
- BSEE with 7 years of applicable work experience or MSEE with 5 years of experience;
- Strong knowledge in measurement theory and measurement skills (VNA, TDR, Real Time Scope, BERT);
- Proficient theory on series equalization, Serdes circuit (FFE/CTLE/DFE) and jitter separation;
- Very familiar with PCIe standards. Knowing 25G/56G/112G Ethernet and CEI is a plus;
- Good skills on Python coding;
- Experience with at least one PCB layout tools: Cadence Allegro, Mentor Expedition or Altium Protel.
- Participate ASIC digital verification for various IP/SoC projects;
- Create verification plans with designers;
- Develop DV architecture and verification environment;
- Verification execution and sign-off.
- Excellent team working style;
- Solid IP/SoC verification background;
- Mass production for verified IP/SoC;
- Master with 2+ years of working experience in ASIC digital verification;
- Production experience in verification strategies and testplans;
- Familiar with System Verilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage;
- Production experience in ARM buses, such as AXI/AMBA/APB is a plus;
- Familiar with verification tools;
- Experiences in Dsp,Core, trace&debug,Soc is a plus;
- Familiar with Linux, csh/Python or any script languages;
- Good English reading and writing skills.
- Lead the DFT team to support complex SoC design;
- Define, prototype and deploy DFT architectures and efficient DFT flows;
- Work with design team to guarantee high DFT coverage;
- Work with test engineering team in patterns handoff and debug;
- Work with design and system team for post-silicon validation.
- Master degree with 8+ years of industry experience in DFT;
- Good understanding of logic design, synthesis, static timing analysis and CDC;
- Knowledge of industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time;
- Experience in developing DFT specifications and driving DFT architecture and methods for designs;
- Past experience as a team lead (direct management experience preferred);
- Positive mindset, self-driven and good team player;
- Excellent written and oral communication skills in both Chinese and English.
- Build SoC/IP level Spyglass/Synthesis/Timing Analysis/Formality Check/CDC flow;
- Do SoC/IP level synthesis/timing analysis/formality check/CDC check;
- Deliver constraints and closely co-work timing closure with P&R;
- Take some block level RTL coding.
- MSEE with 3+ year experience in digital design experience;
- Relevant experience in complex timing closure;
- Be familiar with DC/PT/formality check tools;
- Be familiar with Scripts language such as Tcl, Perl, etc.;
- RTL coding experience is a plus.
- Support EDA design flow and EDA tool, including digital and analog design flow;
- Support timing characterization flow for stand cell, I/O, memory, analog IP;
- Support TCAD to setup and debug foundry technology files;
- Perl/SKill/TCL script support.
- BSEE with minimum 1 year or MSEE with minimum 1 year of experience;
- Familiar with EDA design flow for mixed-signal design;
- Familiar with Computer languages such as C, C++, perl/TCL/C-shell.
- Serdes communication system algorithm design;
- Digital signal processing of mixed-signal system;
- Analog circuit behavior modeling;
- Support verification of mixed-signal system.
- MS or PhD degree in EE or Communication with an emphasis on digital signal processing and one of the following: communications systems or analog/mixed-signal integrated circuit design;
- Familiar with commercial wireline or wireless communication specifications;
- Familiar with the following programming languages: Matlab/simulink, C/C++;
- Familiar with digital signal processing algorithm and practical implementation skills including adaptive signal processing, multi-rate signal processing, linear regression, knowledge of concepts such as cost functions, etc.;
- Experience in algorithm development for software and/or hardware;
- Strong communication skills and ability to work in distributed development environment.
- Perform analog and mixed-signal physical design;
- Perform layout verification (DRC, LVS);
- Modify and verify in-house DRC & LVS command files.
- BS with above 2 years of industry IC layout experience, BSEE is preferred;
- Good understanding of basic electronic principles dealing with circuit and layout design;
- Prior experience with 16nm/14nm/12nm/7nm high speed circuit or DDR or Serdes is a plus;
- Familiar with IC layout methodologies and flows;
- Familiar with CAD tools such as Cadence virtuoso layout, PCELLs, Calibre physical verification;
- Familiar with Calibre DRC & LVS command files;
- Prior experience in stand-cell built is a plus.
- Writing micro-architecture definition/IC design spec;
- RTL coding for logic modules;
- Simulation/Verification of functionalities at both module level and top level;
- Do module level synthesis/timing analysis;
- Writing complete design/verification reports;
- Silicon debug of the related module functionalities;
- Writing test patterns for production tests.
- MSEE with minimum 2 year experience of digital design experience;
- Relevant experience in high-speed and low power digital design is must;
- Solid knowledge in digital design building blocks (eg. Data-path, Synchronizer, FIFO, etc.);
- Strong skills of Verilog RTL coding and verification and debug;
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;
- Relevant experience in DDR interface design is a plus;
- Self-motivated and team player.
We are looking for an experienced Switch Power IC design engineer to develop a high efficiency Buck PMIC for next generation DDR application. The Job includes but not limits to below items:
- Buck behavior model build up, key parameters simulation, fine tune and verification;
- Define specifications of blocks and create design documentation;
- All function block circuit level design, simulation and verification;
- Supervise layout floor plan and design of each function blocks;
- Silicon evaluation test, characterization and debugging;
- Production test development support.
- BSEE or above with at least 2 years of experience in switch power IC development;
- Experience in switch power supply behavior model build up;
- Experience in Buck power IC circuit design;
- Ability to supervise layout floor plan and design;
- Good understanding of BCD process, model for switch power supply IC design;
- Proficiency of EDA design tools (Simplis, Spectre, HSPICE, etc);
- Good Lab experience in switch power IC testing;
- Good verbal and written communication and presentation skills, positive attitude;
- Willing to take challenges and to solve difficult technical problems;
- Quick learner.