职位描述
- Serdes communication system algorithm design;
- Digital signal processing of mixed-signal system;
- Analog circuit behavior modeling;
- Support verification of mixed-signal system.
岗位要求
- MS or PhD degree in EE or Communication with an emphasis on digital signal processing and one of the following: communications systems or analog/mixed-signal integrated circuit design;
- Familiar with commercial wireline or wireless communication specifications;
- Familiar with the following programming languages: Matlab/simulink, C/C++;
- Familiar with digital signal processing algorithm and practical implementation skills including adaptive signal processing, multi-rate signal processing, linear regression, knowledge of concepts such as cost functions, etc.;
- Experience in algorithm development for software and/or hardware;
- Strong communication skills and ability to work in distributed development environment.
职位描述
- Writing micro-architecture definition/IC design spec;
- RTL coding for logic modules;
- Simulation/Verification of functionalities at both module level and top level;
- Do module level synthesis/timing analysis;
- Writing complete design/verification reports;
- Silicon debug of the related module functionalities;
- Writing test patterns for production tests.
岗位要求
- MSEE with minimum 2 year experience of digital design experience;
- Relevant experience in high-speed and low power digital design is must;
- Solid knowledge in digital design building blocks (eg. Data-path, Synchronizer, FIFO, etc.);
- Strong skills of Verilog RTL coding and verification and debug;
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;
- Relevant experience in DDR interface design is a plus;
- Self-motivated and team player.
职位描述
- Support EDA design flow and EDA tool, including digital and analog design flow;
- Support timing characterization flow for stand cell, I/O, memory, analog IP;
- Support TCAD to setup and debug foundry technology files;
- Perl/SKill/TCL script support.
岗位要求
- BSEE with minimum 1 year or MSEE with minimum 1 year of experience;
- Familiar with EDA design flow for mixed-signal design;
- Familiar with Computer languages such as C, C++, perl/TCL/C-shell.
职位描述
- Write micro-architecture definition/IC design spec;
- Write RTL coding for block or top level;
- Do IP level synthesis/timing analysis/formality check/CDC check /code coverage check;
- Assist on verification engineer to complete module and top level simulation and verification;
- Debug RTL/Gate Level waveform at module or top level;
- Do Silicon debugging of the related module functionalities and provide ECO solution accordingly.
岗位要求
- MSEE with more than 5 years experience in digital design;
- Relevant experience in high speed IO IP design. PCIe design experience is a plus;
- Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO;
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;
- Strong skills of Script and be familiar with TCL, Perl, etc.;
- Self-motivated, good team work spirit and good communication skills.
职位描述
- Work out test plan with designer;
- Develop test hardware and software on ATE to support mass production and engineering;
- Correlate test result between ATE and bench;
- Do ATE test repeatability and distribution study to make sure the robustness of the testing;
- Support DE/AE to fulfill device evaluation for new product on functional patterns and DC/AC parameters to guarantee the parameters meet design target or datasheet spec;
- Transfer ATE test hardware and software to subcon and share the knowledge to manufacturing engineers;
- Sustain the production line by trouble shooting any abnormality in the line;
- Optimize ATE testing or migrate to suitable platform to improve test coverage, reduce test time/cost and enhance testing performance.
岗位要求
- Bachelor degree or above, major in Electronic Engineering or related;
- 2+ years of consumer electronics working experience;
- Be familiar with basic knowledge about digital and analog circuit and C language or other programming language;
- Have experience in IC testing or design, FPGA experience, high speed test experience, ATE debugging skill;
- Good written and oral communications skills;
- Good sense of responsibility and positive working attitude.
职位描述
- Perform analog and mixed-signal physical design;
- Perform layout verification (DRC, LVS);
- Modify and verify in-house DRC & LVS command files.
岗位要求
- BS with above 2 years of industry IC layout experience, BSEE is preferred;
- Good understanding of basic electronic principles dealing with circuit and layout design;
- Prior experience with 16nm/14nm/12nm/7nm high speed circuit or DDR or Serdes is a plus;
- Familiar with IC layout methodologies and flows;
- Familiar with CAD tools such as Cadence virtuoso layout, PCELLs, Calibre physical verification;
- Familiar with Calibre DRC & LVS command files;
- Prior experience in stand-cell built is a plus.
职位描述
- Write micro-architecture definition/IC design spec;
- Write RTL coding for block or top level;
- Do IP level synthesis/timing analysis/formality check/CDC check/code coverage check;
- Assist on verification engineer to complete module and top level simulation and verification;
- Debug RTL/Gate Level waveform at module or top level;
- Do silicon debugging of the related module functionalities and provide ECO solution accordingly.
岗位要求
- MSEE with more than 5 years experience of digital design;
- Relevant experience in DDR memory controller IP design or IP integration;
- Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO;
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;
- Strong skills of Script and be familiar with TCL, Perl, etc.;
- Self-motivated, good team work spirit and good communication skills.
职位描述
- DSP Compiler Architecture definition;
- Lead and participate in the DSP Compiler Development;
- Collaborate with peers in SW Architecture and DSP Hardware team.
岗位要求
- MSEE with 8+ year experience or PhD with 5+ year experience of system software development or design;
- In depth knowledge of CPU/GPU/NPU architecture;
- Strong programming skills and knows how to optimize program to reach maximum performance under given hardware;
- Strong knowledge of hardware-software co-design and knows how to optimize the whole design to achieve high efficiency;
- Experience in building compiler using LLVM or equivalent.
职位描述
The candidate will be responsible for design and characterization of high-speed analog/mixed-signal circuit blocks for ultra-high speed SerDes.
Detailed responsibilities include:
- Taking an active role in block design implementation, verification and quality check;
- Supervising layout designers on physical implementation of SerDes circuits;
- Creating design documents for analog/mixed-signal design methodology.
岗位要求
- Minimum MSEE with 3+ years of relevant industry experience;
- Hands-on experience in designing one or more of the following blocks: CTLE, DFE, PLL, CDR, TI SAR-ADC, analog/digital circuit calibration algorithm and implementation;
- Self-driven, excellent problem solving and analytical skill, good communication skills and a strong team player;
- Deep understanding of SerDes design and architecture such as adaptive signal processing/communication systems is a plus.
职位描述
We are looking for an experienced switch power IC design engineer to develop a high efficiency Buck PMIC for next generation DDR application. The job includes but not limits to below items:
- Buck behavior model build up, key parameters simulation, fine tune and verification;
- Define specifications of blocks and create design documentation;
- All function block circuit level design, simulation and verification;
- Supervise layout floor plan and design of each function blocks;
- Silicon evaluation test, characterization and debugging;
- Production test development support.
岗位要求
- BSEE or above with at least 2 years of experience in switch power IC development;
- Experience in switch power supply behavior model build up;
- Experience in Buck power IC circuit design;
- Ability to supervise layout floor plan and design;
- Good understanding of BCD process, model for switch power supply IC design;
- Proficiency of EDA design tools (Simplis, Spectre, HSPICE, etc);
- Good Lab experience in switch power IC testing;
- Good verbal and written communication and presentation skills, positive attitude;
- Willing to take challenges and to solve difficult technical problems;
- Quick learner.