社会招聘


职位描述


  • Lead physical design of projects, build and manage physical design team;
  • Coordinate with different teams to close design issues, such as front-end team, DFT team, and package team;
  • Responsible for achievable die size, meet design requirements, drive design closure and sign-off checks;
  • Responsible for full chip floorplan & partition, pin assign, feedthrough & repeater insertion; release floorplan to block level implementation;
  • Develop top level physical design flow.

岗位要求


  • Bachelor or Master Degree in Engineering (Microelectronics, Electronics);
  • 10+ years of hands on experience in large scale ASIC chip physical design;
  • Experienced with large scale full chip floorplan;
  • Familiar with top-down design methodology;
  • Experience on project and team management;
  • Good teamwork and communication skills;
  • Proficient with scripting/programming (TCL, Perl, shell script, Python);
  • Language: Good English read/write.

 

申请职位

职位描述


  • Lead the DFT team to support complex SoC design;
  • Define, prototype and deploy DFT architectures and efficient DFT flows;
  • Work with design team to guarantee high DFT coverage;
  • Work with test engineering team in patterns handoff and debug;
  • Work with design and system team for post-silicon validation.

岗位要求


  • Master degree with 8+ years of industry experience in DFT;
  • Good understanding of logic design, synthesis, static timing analysis and CDC;
  • Knowledge of industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time;
  • Experience in developing DFT specifications and driving DFT architecture and methods for designs;
  • Past experience as a team lead (direct management experience preferred);
  • Positive mindset, self-driven and good team player;
  • Excellent written and oral communication skills in both Chinese and English.

申请职位

职位描述


  • Build SoC/IP level Spyglass/Synthesis/Timing Analysis/Formality Check/CDC flow;
  • Do SoC/IP level synthesis/timing analysis/formality check/CDC check;
  • Deliver constraints and closely co-work timing closure with P&R;
  • Take some block level RTL coding.

岗位要求


  • MSEE with 3+ year experience in digital design experience;
  • Relevant experience in complex timing closure;
  • Be familiar with DC/PT/formality check tools;
  • Be familiar with Scripts language such as Tcl, Perl, etc.;
  • RTL coding experience is a plus.

申请职位

职位描述


  • Serdes communication system algorithm design;
  • Digital signal processing of mixed-signal system;
  • Analog circuit behavior modeling;
  • Support verification of mixed-signal system.

岗位要求


  • MS or PhD degree in EE or Communication with an emphasis on digital signal processing and one of the following: communications systems or analog/mixed-signal integrated circuit design;
  • Familiar with commercial wireline or wireless communication specifications;
  • Familiar with the following programming languages: Matlab/simulink, C/C++;
  • Familiar with digital signal processing algorithm and practical implementation skills including adaptive signal processing, multi-rate signal processing, linear regression, knowledge of concepts such as cost functions, etc.;
  • Experience in algorithm development for software and/or hardware;
  • Strong communication skills and ability to work in distributed development environment.

申请职位

职位描述


  • Writing micro-architecture definition/IC design spec;
  • RTL coding for logic modules;
  • Simulation/Verification of functionalities at both module level and top level;
  • Do module level synthesis/timing analysis;
  • Writing complete design/verification reports;
  • Silicon debug of the related module functionalities;
  • Writing test patterns for production tests.

岗位要求


  • MSEE with minimum 2 year experience of digital design experience;
  • Relevant experience in high-speed and low power digital design is must;
  • Solid knowledge in digital design building blocks (eg. Data-path, Synchronizer, FIFO, etc.);
  • Strong skills of Verilog RTL coding and verification and debug;
  • Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;
  • Relevant experience in DDR interface design is a plus;
  • Self-motivated and team player.

申请职位

职位描述


  • Support EDA design flow and EDA tool, including digital and analog design flow;
  • Support timing characterization flow for stand cell, I/O, memory, analog IP;
  • Support TCAD to setup and debug foundry technology files;
  • Perl/SKill/TCL script support.

岗位要求


  • BSEE with minimum 1 year or MSEE with minimum 1 year of experience;
  • Familiar with EDA design flow for mixed-signal design;
  • Familiar with Computer languages such as C, C++, perl/TCL/C-shell.

 

申请职位

职位描述


  • Write micro-architecture definition/IC design spec;
  • Write RTL coding for block or top level;
  • Do IP level synthesis/timing analysis/formality check/CDC check /code coverage check;
  • Assist on verification engineer to complete module and top level simulation and verification;
  • Debug RTL/Gate Level waveform at module or top level;
  • Do Silicon debugging of the related module functionalities and provide ECO solution accordingly.

岗位要求


  • MSEE with more than 5 years experience in digital design;
  • Relevant experience in high speed IO IP design. PCIe design experience is a plus;
  • Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO;
  • Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;
  • Strong skills of Script and be familiar with TCL, Perl, etc.;
  • Self-motivated, good team work spirit and good communication skills.

申请职位

职位描述


  • Work out test plan with designer;
  • Develop test hardware and software on ATE to support mass production and engineering;
  • Correlate test result between ATE and bench;
  • Do ATE test repeatability and distribution study to make sure the robustness of the testing;
  • Support DE/AE to fulfill device evaluation for new product on functional patterns and DC/AC parameters to guarantee the parameters meet design target or datasheet spec;
  • Transfer ATE test hardware and software to subcon and share the knowledge to manufacturing engineers;
  • Sustain the production line by trouble shooting any abnormality in the line;
  • Optimize ATE testing or migrate to suitable platform to improve test coverage, reduce test time/cost and enhance testing performance.

岗位要求


  • Bachelor degree or above, major in Electronic Engineering or related;
  • 2+ years of consumer electronics working experience;
  • Be familiar with basic knowledge about digital and analog circuit and C language or other programming language;
  • Have experience in IC testing or design, FPGA experience, high speed test experience, ATE debugging skill;
  • Good written and oral communications skills;
  • Good sense of responsibility and positive working attitude.

申请职位

职位描述


  • Perform analog and mixed-signal physical design;
  • Perform layout verification (DRC, LVS);
  • Modify and verify in-house DRC & LVS command files.

岗位要求


  • BS with above 2 years of industry IC layout experience, BSEE is preferred;
  • Good understanding of basic electronic principles dealing with circuit and layout design;
  • Prior experience with 16nm/14nm/12nm/7nm high speed circuit or DDR or Serdes is a  plus;
  • Familiar with IC layout methodologies and flows;
  • Familiar with CAD tools such as Cadence virtuoso layout, PCELLs, Calibre physical verification;
  • Familiar with Calibre DRC & LVS command files;
  • Prior experience in stand-cell built is a plus.

申请职位

职位描述


  • Write micro-architecture definition/IC design spec;
  • Write RTL coding for block or top level;
  • Do IP level synthesis/timing analysis/formality check/CDC check/code coverage check;
  • Assist on verification engineer to complete module and top level simulation and verification;
  • Debug RTL/Gate Level waveform at module or top level;
  • Do silicon debugging of the related module functionalities and provide ECO solution accordingly.

岗位要求


  • MSEE with more than 5 years experience of digital design;
  • Relevant experience in DDR memory controller IP design or IP integration;
  • Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO;
  • Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;
  • Strong skills of Script and be familiar with TCL, Perl, etc.;
  • Self-motivated, good team work spirit and good communication skills.

申请职位