We are looking for an experienced switch power IC design engineer to develop a high efficiency Buck PMIC for next generation DDR application. The job includes but not limits to below items:
- Buck behavior model build up, key parameters simulation, fine tune and verification;
- Define specifications of blocks and create design documentation;
- All function block circuit level design, simulation and verification;
- Supervise layout floor plan and design of each function blocks;
- Silicon evaluation test, characterization and debugging;
- Production test development support.
- BSEE or above with at least 2 years of experience in switch power IC development;
- Experience in switch power supply behavior model build up;
- Experience in Buck power IC circuit design;
- Ability to supervise layout floor plan and design;
- Good understanding of BCD process, model for switch power supply IC design;
- Proficiency of EDA design tools (Simplis, Spectre, HSPICE, etc);
- Good Lab experience in switch power IC testing;
- Good verbal and written communication and presentation skills, positive attitude;
- Willing to take challenges and to solve difficult technical problems;
- Quick learner.
- Participate ASIC digital verification for various IP/SoC projects;
- Create verification plans with designers;
- Develop DV architecture and verification environment;
- Verification execution and sign-off.
- Excellent team working style;
- Solid IP/SoC verification background;
- Mass production for verified IP/SoC;
- Bachelor with 2+ years of working experience in ASIC digital verification;
- Production experience in verification strategies and testplans;
- Familiar with System Verilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage;
- Production experience in ARM buses, such as AXI/AMBA/APB is a plus;
- Familiar with verification tools ;
- Familiar with Linux, csh/Python or any script languages;
- Good English reading and writing skills.
- Code development and code review on the PCIe/CXL driver;
- Daily debug of PCIe/CXL driver code;
- Interaction with hardware team and other software component teams.
- MSEE in Computer Science, Computer Engineering or related fields;
- Experience in C/C++ programming language;
- Familiar with Linux driver design;
- Strong skills of device driver coding using C/C++;
- Self-motivated, good team work spirit and good communication skills;
- Familiar with GPU driver development is a plus.
The candidate will be responsible for design and characterization of high-speed analog/mixed-signal circuits for ultra-high speed Serdes.
Detailed responsibilities include:
- Participating in Serdes architecture design and block specification;
- Taking an active role in block design implementation, verification and quality check;
- Supervising layout designers on physical implementation of Serdes circuits;
- Monitoring junior design engineer to help them complete design task;
- Creating design documents for analog/mixed-signal design methodology.
- Minimum MSEE with 7+ years of relevant industry experience;
- Deep understanding of Serdes design and architecture;
- Hands-on experience of CTLE, DFE, PLL, CDR, TI SAR-ADC, analog/digital circuit calibration algorithm and implementation;
- Direct experience in Serdes bring up, debug and characterization using lab equipment;
- Able to assume responsibility for a variety of technical tasks and to work independently;
- Self-driven, excellent problem solving and analytical skill, good communication skills and a strong team player.
- Define and develop package solution for high speed, high power and large pin count device in a cross-function team;
- Design rule development and implementation of in-house packaging layout to meet product requirements;
- Interface with vendors on process optimization, chip characterization and failure analysis for volume production;
- PI/SI analysis on full chip and critical IPs at package level;
- Drive new technology development such as multi-die, advanced substrate, design for manufacturability and design for reliability, as a collaborative effort with vendors.
- Education: Bachelor Degree or above, Master is preferred. Major in Electrical Engineering/Microwave/Microelectronics/Physics etc.;
- Hands on experiences with layout of FCBGA, MCM, SiP, WLBGA etc. and optimization for ball count and power grid;
- Experience on design of very large form factor flip chip package with high substrate layer count;
- Experience with high-speed IO interfaces design and PI/SI analysis, such as DDR and PCIe is preferred;
- Experience on mechanical and thermal analysis and control, knowledge on mechanical and thermal reliability is a plus;
- Capability of driving package roadmap to meet future products on advanced nodes.
- Build and execute verification for digital IC;
- Study design specification and extract the verification items;
- Create the verification plan;
- Develop verification platform based on UVM;
- Co-work with design team to clean the bugs in bench or design;
- Run verification regression test;
- Collect and analysis coverage and help convergence.
- MSEE with 2+ years working experience in UVM based IC verification;
- Good team working style;
- Good at Verilog/System Verilog coding;
- Good at function coverage development is a plus;
- Good at assertion based verification is a plus;
- Familiarity with C programming is a plus;
- Familiarity with Python programming is a plus;
- Familiarity with DDR SDRAM is a great plus.
- 开发，维护以及改进自动化测试框架 ；
- 熟悉 C/C++编程语言；
- Design, simulation and verification of high speed CMOS analog and mixed-signal circuits;
- Co-work with layout engineer for physical implementation;
- Help define specifications of IC blocks and create design documentation;
- Silicon test, characterization and debugging.
- Solid knowledge and experience in high speed analog and mixed-signal circuit design;
- Experience in high speed I/O related area (Serdes, Transmitter, Receiver, DDR I/O interface, etc.) is a plus;
- Good understanding of deep submicron CMOS technology process and device physics;
- Proficiency of EDA design tools (Virtuoso, Spectre, HSPICE, AMS, etc.);
- Experiences in Verilog, Verilog-A, Python, and/or Matlab.
- Write micro-architecture and integration design spec;
- Write RTL coding for core and bus standard trace logic, monitor signal map, debug control, etc.;
- Do IP level Linting/CDC check/synthesis/timing analysis/formality check;
- Assist on verification engineer to complete module to top level verification and debugging;
- Debug RTL and Gate Level waveform at top level to provide ECO solution in case of bug fixes;
- Take silicon debugging of the related module functionalities.
- MSEE with 2+ year experience of digital design;
- Strong skills of Verilog RTL coding, simulation debug and ECO changes with netlist database;
- Hands on experience in EDA tools such as VCS, Spyglass, DC, PT, Equivalence check, etc.;
- Basic skills of script and be familiar with Shell, Perl, Python, etc.;
- Self-motivated, good team work spirit and communication skills;
- Following working experiences will be one advantage：
- Experience in CPU or DSP design;
- Experience in AXI/AHB/APB protocols and ARM-based fabric design;
- Experience in core or bus trace and debug, signal monitoring, MIPI, PCIe, JTAG related.
- Develop virtual platform system, both creating new models as well as integrating third party models;
- Develop and test new virtualization features in QEMU, KVM;
- Validate implemented module from unit to unit integrated level;
- Work closely with Software, SOC Design, and SOC Design Verification teams.
- Bachelor's degree in Computer Science;
- 3+ years’ experience in SOC modeling, instruction set simulator development, or embedded software development;
- Strong understanding of computer architecture concepts;
- Proficient in C/C++ and scripting languages such as Python and Unix shell script;
- Good communication skill, team work spirit, self-motivated; Preferred Qualification:
- Familiarity with simulators such as Fast Models, Virtualizer, Virtual System Platform, QEMU;
- Proficient in SystemC, Verilog, System Verilog, and Assembly;
- Familiarity with industry standard technologies like AXI, PCIe, DDR;
- Familiarity with RISC-V instruction set architecture.