数字设计工程师

职位描述：

• Write Micro-Architecture and Integration Design Spec; 
• Write RTL coding for core and bus standard trace logic, monitor signal map, debug control, etc.; 
• Do IP level Linting / CDC check / synthesis / timing analysis / formality check; 
• Assist on Verification Engineer to complete module to top level verification and debugging; 
• Debug RTL and Gate Level waveform at top level to provide ECO solution in case of bug fixes; 
• Take silicon debugging of the related module functionalities.

岗位要求：

• MSEE or above with experience of digital design; 
• Strong skills of Verilog RTL coding, simulation debug and ECO changes with netlist database; 
• Hands on experience in EDA tools such as VCS, Spyglass, DC, PT, Equivalence check, etc.; 
• Basic skills of script and be familiar with Shell, Perl, Python, etc.; 
• Self-motivated, good team work spirit and communication skills; 
• Following working experiences will be one advantage:  
  Experience in DDR/ CPU/ GPU design;    
  Experience in AXI/AHB/APB protocols and ARM-based fabric design;  
  Experience in core or bus trace and debug, signal monitoring, PCIe, JTAG related. 

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