模拟设计工程师

职位描述：

• Design, evaluate and verify CMOS analog circuits ( PLL、DDR、USB、HDMI、ADAC、VDAC); 
• Oversee layout and verification activities which include floor plan, LVS and DRC.

岗位要求：

• Bachelor degree or Master degree in ASIC Design Relevant;   
• Experience in RF/Analog IC design;   
• Good fundamental in analysis and design of analog / mixed-signal circuits; 
• Experience in Verilog, AHDL and/or Matlab; 
• Ability to do layout and provide verification/debugging guidance; 
• Solid knowledge of EDA design tools (Analog artist, spectre, HSPICE and nc-verilog ...); 
• Familiar with Computer languages such as C, C++, perl;   
• Experience in any of the following areas is preferred: PLL, high-speed I/O’s;   
• Good communication skills and Good oral/written English.

申请职位