Montage Semiconductor, Inc., located at 3955 Johns Creek Ct., Suite 300, Suwanee, GA 30024, is seeking a Senior Digital Design Engineer, responsible for various circuit design process, from RTL coding in System Verilog, logical and mixed-signal simulations and verification, and optimization for Power, Performance, and Area (PPA) targets. Job duties include the following:
Writing microarchitecture and performing RTL Coding in System Verilog to record the behavior of complex digital circuits at a higher level of abstraction;
Designing and writing RTL coding using System Verilog from inception through performance cycle;
Conducting Logical and Mixed-Signal Simulations to verify the correctness of designs and check functional correctness to ensure overall system behavior matches expectations and meets timing requirements;
Using design flow and design tools for simulation, debugging, synthesis, timing analysis, and running various RTL tools (Synthesis, Lint, CDC/RDC, DFT) to identify and fix potential issues in the code in order to meet Power, Performance, and Area (PPA) targets;
Performing optimization to achieve PPA as defined in block specifications;
Validating module design for syntax errors through Lint, and clock/reset mismatch through CDC and RDC tools;
Implementing fine-grain power gating for critical paths in the module to reduce leakage, and improving performance; and
Collaborating with other engineers such as verification engineer, validation engineer, and software engineer to ensure the successful integration of digital circuits into the larger system.
Require a Master of Science degree in Electrical Engineering, Electronics Engineering, and 2 years of experience in digital design engineer, electronic design engineer, or related. Must have skills of Cadence tools (Virtuoso, Innovus, SimVision), Synopsys Tools and knowledge of Verilog/System Verilog, digital design, programming in C++ and Python. Send resume to GAHR@montage-tech.com.