M88DR5RCD01 (Gen1 DDR5 RCD)
DDR5 RDIMM
M88DR5RCD01 (Gen1 DDR5 RCD)

M88DR5RCD01 is a JEDEC-compliant Gen1 DDR5 Registering Clock Driver (RCD), supporting data rates up to 4800 MT/s and VDD supply of 1.1V. It is a two-channel RCD designed for driving and buffering the Command/Address (CA) bus, Chip Selects, and clock between the host controller and the DDR5 SDRAMs. The RCD can be used independently as a central buffer on an RDIMM or used in conjunction with Gen1 DDR5 data buffers (DBs) on an LRDIMM to enable higher capacity and lower power consumption for memory systems.

The left image shows the application of RCD01 on the DDR5 RDIMM as an example.

Features
  • Fully compliant with JEDEC DDR5RCD01 specificationFully compliant with JEDEC DDR5RCD01 specification
  • Speed up to 4800 MT/sSpeed up to 4800 MT/s
  • 1.1V VDD and 1.0V VDDIO voltages1.1V VDD and 1.0V VDDIO voltages
  • Two channel 1:2 registering buffer for address and control signalsTwo channel 1:2 registering buffer for address and control signals
  • Integrated PLL clock driver distributing one differential clock pair to five differential pairs per channelIntegrated PLL clock driver distributing one differential clock pair to five differential pairs per channel
  • Dual chip selectsDual chip selects
  • Parity checking across CA and DPAR separately on two sub-channelsParity checking across CA and DPAR separately on two sub-channels
  • Output characteristics configurable through control registersOutput characteristics configurable through control registers
  • CA, CS and DFE training modes and Dual Frequency supportedCA, CS and DFE training modes and Dual Frequency supported
  • Sideband bus interface supporting I²C and I3C Basic modesSideband bus interface supporting I²C and I3C Basic modes
  • Power saving modes: PDE power down, Self refresh w/wo Clock Stop modesPower saving modes: PDE power down, Self refresh w/wo Clock Stop modes
  • Green package: 240-ball FCBGAGreen package: 240-ball FCBGA
Applications

DDR5 RDIMM and DDR5 LRDIMM

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