With the boost of the DDR5 data rate, the frequency of the clock signal becomes higher and higher, and the signal integrity issue of the clock becomes more and more challenging. As the DDR5 data rate reaches 6400MT/s and above, the memory modules such as UDIMMs and SODIMMs used in desktop and notebook computers, will need an on-DIMM clock driver to buffer and re-drive the clock signal of the memory modules, to meet the signal integrity and reliability requirement of the high-speed clock signal.

Montage’s CKD chip is primarily used on DDR5 client memory modules including CUDIMM, CSODIMM, and CAMM, to buffer the clock signals between the client central processor and DRAM, enhancing the integrity and reliability of high-speed clock signals. The chip is compliant with the JEDEC DDR5CKD01 specification and supports data rates up to 7200MT/s. It provides dual-sided bus address access and supports I²C and I3C interfaces. By configuring register control words, the chip can change its output signal characteristics to match various DIMM network topologies. Its power consumption can also be reduced by disabling unused output signals.